A programmable logic array(which is called PLA in the following description) is disposed in various kinds of logic LSIs such as the one in a microprocessor and is used as a control circuit and a decoding circuit, and is provided with an input decoder for decoding an input signal to reduce the number of product term lines and reduce the size of the area of the logic array.
FIG. 1 is a view showing the construction of PLA provided with an input decoder. In FIG. 1, the PLA is constituted by two bit input decoders 1 each receiving two corresponding input signals from input signals x.sub.1 to x.sub.N and providing four decoding outputs by taking a logic operation of the two corresponding input signals, an array region (which is called AND plane in the following description) 3 for producing logic product terms S.sub.1 and S.sub.m with respect to decoding outputs d.sub.1 to d.sub.m of the respective input decoders 1, and an array region 5 for receiving the respective logic product terms S.sub.1 to S.sub.m produced on the AND plane and producing logic sum terms O.sub.1 to O.sub.l with respect to the respective logic product terms S.sub.1 to S.sub.m, thereby outputting product and sum signals of the input signals x.sub.1 to x.sub.N.
FIG. 2 is a view showing an example of the detailed construction of one of the input decoders 1 of the PLA shown in FIG. 1. The one input decoder 1 of FIG. 2 is constituted by a decoder for receiving input signals x.sub.1 and x.sub.2 for example, and the other input decoders 1 are similarly constructed.
In FIG. 2, the input decoder 1 is constituted by a NOR gate 7a for inputting the input signals x.sub.1 and x.sub.2, a NOR gate 7b for inputting the input signal x.sub.1 and an inverted signal of the input signal x.sub.2 inverted through an inverter 9b, a NOR gate 7c for inputting an inverted signal of the input signal x.sub.1 inverted through an inverter 9a and the input signal x.sub.2, and a NOR gate 7d for inputting the respective inverted signals of the input signals x.sub.1 and x.sub.2 inverted through the inverters 9a and 9b.
In FIG. 2, the input decoder 1 is constituted by using a gate circuit so that it is very difficult to perform high integration of the input decoder 1, which becomes more serious with the increase of the number of input signals.
FIG. 3 is a view showing the construction of a PLA provided with an input decoder 11 for receiving input signals x.sub.1 and x.sub.N and supplying decoding outputs d.sub.1 and d.sub.2N to an AND plane 3 by performing a logic operation of the input signals. FIG. 4 is a view showing an example of the detailed construction of the input decoder 11 shown in FIG. 3. In FIG. 3, the same or corresponding portions as those of FIG. 1 are designated by the same reference numerals, and are thereby not described in detail in the following description.
In FIG. 4, the input decoder 11 has N input lines 13 for receiving corresponding input signals x.sub.1 to x.sub.N, N input lines 17 for receiving inverted input signals provided by inverting the corresponding input signals by inverters 15, and a plurality of output lines 21 connected to a power source V.sub.DD through FETs 19 of P-channel type having gate terminals connected to ground. The N input lines 13, the N input lines 17 and the plurality of output lines 21 are arranged in the shape of a matrix. As shown in FIG. 5, FETs 23 of N-channel type are disposed at predetermined intersections of the respective input lines 13, 17 and the output lines 21 to provide a logic similar to the one of the input decoder 1 shown in FIG. 2 from the output lines 21 with respect to the respective input signals.
The input decoder 11 of FIG. 4 is constituted by a matrix structure so that the integrated degree is high in comparison with the input decoder 1 using the gate circuit of FIG. 2.
However, when two bit decoding is performed with respect to N input signals where N is an even number, it is necessary to dispose 2N input lines 13 and 17, and 2N output lines 21 so that the area of the input decoder has 2N (the number of input lines) times 2N (the number of output lines)=4N.sup.2 and is therefore increased in proportion to square of the number of input signals.
In FIG. 4, the regions enclosed by dotted lines are regions in which the FETs 23 are not formed, and the ratio of these enclosed regions to the entire area of the decoder is increased as the number of input signals is increased, thereby increasing such useless regions as the size of the input decoder 11 is increased.
Further, the inverters 15 for inverting the input signals have output terminals directly connected to the input lines 17 so that it is necessary to increase the sizes of the inverters 15 when the structure of the decoder is made large as the number of input signals is increased.
Accordingly, it is difficult to attain high integration even in the input decoder 11 having the matrix structure shown in FIG. 4.
As mentioned above, it is difficult to attain high integration of the PLA provided with the input decoder, even when the input decoder is constructed by using the logic gate circuit shown in FIG. 2, or even when the input decoder is constructed by using the matrix structure as shown in FIG. 4.